| MRC |
Requirement Statement |
Characteristics |
| CQWX |
OUTPUT LOGIC FORM |
TRANSISTOR-TRANSISTOR LOGIC |
| TTQY |
TERMINAL TYPE AND QUANTITY |
14 FLAT LEADS |
| CQSZ |
INCLOSURE CONFIGURATION |
FLAT PACK |
| CWSG |
TERMINAL SURFACE TREATMENT |
SOLDER |
| CSSL |
DESIGN FUNCTION AND QUANTITY |
2 GATE, AND-OR |
| TEST |
TEST DATA DOCUMENT |
03640-6062966 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CZEQ |
TIME RATING PER CHACTERISTIC |
15.50 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CBBL |
FEATURES PROVIDED |
HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS |
| CZEN |
VOLTAGE RATING AND TYPE PER CHARACTERISTIC |
5.5 VOLTS NOMINAL POWER SOURCE |
| CQSJ |
INCLOSURE MATERIAL |
CERAMIC |
| AFGA |
OPERATING TEMP RANGE |
-55.0 TO 125.0 DEG CELSIUS |
| AFJQ |
STORAGE TEMP RANGE |
-65.0 TO 150.0 DEG CELSIUS |
| ADAQ |
BODY LENGTH |
0.380 INCHES MAXIMUM |
| CQZP |
INPUT CIRCUIT PATTERN |
DUAL 2 WIDE 2 INPUT |
| ADAU |
BODY HEIGHT |
0.075 INCHES MAXIMUM |
| ADAT |
BODY WIDTH |
0.200 INCHES MAXIMUM |
